A Redundant Adder Structure Suitable for the New Generation Reconfigurable Fpga Architectures

dc.authorid	TR14575	en_US
dc.authorid	TR6127	en_US
dc.contributor.author	Cini, Ugur
dc.contributor.author	Morgul, Avni
dc.date.accessioned	2015-04-06T07:55:50Z
dc.date.available	2015-04-06T07:55:50Z
dc.date.issued	2011
dc.department	İstanbul Beykent Üniversitesi	en_US
dc.description.abstract	Arithmetic operations are generally slowest operations in digital design which is the bottleneck in most of the systems. Optimizing adder circuits provides faster performance in arithmetic circuits. Field Programmable Gate Arrays (FPGA) are very popular to implement logic circuits. 6-input Look-Up Table (LUT) devices are on the market which dramatically increases the performance. In this paper, alternative addition structures, based on redundant carry-free arithmetic and suitable for 6 input LUT devices, are presented. A new double carry-save addition architecture is proposed, which reduces the critical path of the addition process for 6-input LUT devices.	en_US
dc.identifier.citation	Journal of Science and Technology 4 (1), 2011, 38 - 50	tr_TR
dc.identifier.issn	1307-3818
dc.language.iso	en	en_US
dc.publisher	Beykent Üniversitesi	tr_TR
dc.relation.publicationcategory	Makale - Ulusal Hakemli Dergi - Kurum Öğretim Elemanı	en_US
dc.subject	FPGA	tr_TR
dc.subject	Redundant Arithmetic	tr_TR
dc.subject	Multilevel Logic	tr_TR
dc.title	A Redundant Adder Structure Suitable for the New Generation Reconfigurable Fpga Architectures	en_US
dc.type	Article	en_US

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