A Redundant Adder Structure Suitable for the New Generation Reconfigurable Fpga Architectures
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Tarih
2011
Yazarlar
Dergi Başlığı
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Cilt Başlığı
Yayıncı
Beykent Üniversitesi
Erişim Hakkı
Özet
Arithmetic operations are generally slowest operations in digital design which is the bottleneck in most of the systems. Optimizing adder circuits provides faster performance in arithmetic circuits. Field Programmable Gate Arrays (FPGA) are very popular to implement logic circuits. 6-input Look-Up Table (LUT) devices are on the market which dramatically increases the performance. In this paper, alternative addition structures, based on redundant carry-free arithmetic and suitable for 6 input LUT devices, are presented. A new double carry-save addition architecture is proposed, which reduces the critical path of the addition process for 6-input LUT devices.
Açıklama
Anahtar Kelimeler
FPGA, Redundant Arithmetic, Multilevel Logic
Kaynak
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Sayı
Künye
Journal of Science and Technology 4 (1), 2011, 38 - 50
