Impact of Recipe Restrictions on Photolithography Toolsets in an ASIC Fabrication Environment

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dc.contributor.authorKabak, Kamil Erkan
dc.contributor.authorHeavey, Cathal
dc.contributor.authorCorbett, Vincent
dc.contributor.authorByrne, P. J.
dc.date.accessioned2024-03-13T10:32:54Z
dc.date.available2024-03-13T10:32:54Z
dc.date.issued2013
dc.departmentİstanbul Beykent Üniversitesien_US
dc.description.abstractIn this paper, a detailed discrete event simulation model is used to better understand the effects of recipe constraints resulting from process restrictions and tool capabilities on overall average cycle time performance of a photolithography area and on average cycle times of individual mask layers. The study is motivated by the industry, in which engineers have to frequently make decisions on tool qualifications and recipe coverage. An experimental procedure is developed and implemented to show the impact of different levels of tool paths on photolithography toolsets. The simulation results show that increasing the number of tool paths decreases the overall average photolithography cycle time for particular wafer loading levels. Also, as start volumes increase, toolset utilizations increase and the impact of single-path tools on average cycle times increases. Immature processes and low-use processes tend to have more single paths and thus suffer higher average cycle times accordingly. Furthermore, it is reported that average cycle time decreases significantly under multiple process environments due to the lower impact of single paths.en_US
dc.identifier.doi10.1109/TSM.2012.2220572
dc.identifier.endpage68en_US
dc.identifier.issn0894-6507
dc.identifier.issn1558-2345
dc.identifier.issue1en_US
dc.identifier.scopus2-s2.0-84873400577en_US
dc.identifier.scopusqualityQ1en_US
dc.identifier.startpage53en_US
dc.identifier.urihttps://doi.org/10.1109/TSM.2012.2220572
dc.identifier.urihttps://hdl.handle.net/20.500.12662/3648
dc.identifier.volume26en_US
dc.identifier.wosWOS:000314683400008en_US
dc.identifier.wosqualityQ3en_US
dc.indekslendigikaynakWeb of Scienceen_US
dc.indekslendigikaynakScopusen_US
dc.language.isoenen_US
dc.publisherIEEE-Inst Electrical Electronics Engineers Incen_US
dc.relation.ispartofIeee Transactions On Semiconductor Manufacturingen_US
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanıen_US
dc.rightsinfo:eu-repo/semantics/closedAccessen_US
dc.subjectASICen_US
dc.subjectphotolithography processen_US
dc.subjectrecipe constraintsen_US
dc.subjecttool pathsen_US
dc.titleImpact of Recipe Restrictions on Photolithography Toolsets in an ASIC Fabrication Environmenten_US
dc.typeArticleen_US

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