Impact of Recipe Restrictions on Photolithography Toolsets in an ASIC Fabrication Environment
Küçük Resim Yok
Tarih
2013
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
IEEE-Inst Electrical Electronics Engineers Inc
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
In this paper, a detailed discrete event simulation model is used to better understand the effects of recipe constraints resulting from process restrictions and tool capabilities on overall average cycle time performance of a photolithography area and on average cycle times of individual mask layers. The study is motivated by the industry, in which engineers have to frequently make decisions on tool qualifications and recipe coverage. An experimental procedure is developed and implemented to show the impact of different levels of tool paths on photolithography toolsets. The simulation results show that increasing the number of tool paths decreases the overall average photolithography cycle time for particular wafer loading levels. Also, as start volumes increase, toolset utilizations increase and the impact of single-path tools on average cycle times increases. Immature processes and low-use processes tend to have more single paths and thus suffer higher average cycle times accordingly. Furthermore, it is reported that average cycle time decreases significantly under multiple process environments due to the lower impact of single paths.
Açıklama
Anahtar Kelimeler
ASIC, photolithography process, recipe constraints, tool paths
Kaynak
Ieee Transactions On Semiconductor Manufacturing
WoS Q Değeri
Q3
Scopus Q Değeri
Q1
Cilt
26
Sayı
1
