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Öğe Basic circuits for multi-valued sequential logic(Springer, 2013) Sarica, Fatma; Morgul, AvniMulti-valued logic circuits were presented as an alternative to well known binary logic. It has the potential of reducing the number of active elements and interconnection lines. More data may be transferred trough a single wire using logic signals having more than two levels. However, in spite of their potential advantages, developments in multi-valued systems are not satisfactory. In particular, it is very difficult to find circuits to implement the multilevel sequential circuits. The flip-flop is the basic building block of sequential circuits and may be used to design sequential circuits such as counter/dividers and other sequential circuits. In this regard, a new multilevel flip-flop, called the AB flip-flop, was developed and published by the authors recently (Sarica and Morgul, Electron Lett 47(5):297-298, 2011). In this paper we present a new latch and restoration circuit which improves the performance of the previously designed flip-flop circuit. It is also shown that any sequential circuit may be implemented by using this flip-flop.Öğe A current-mode multi-valued adder circuit for multi-operand addition(Taylor & Francis Ltd, 2011) Cini, Ugur; Morgul, AvniStatic CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 mu m technology. As an example of application, an 8 x 8 bit multiplier circuit is designed and simulated using HSPICE.Öğe High Performance 16-Bit MCML Multiplier(IEEE, 2009) Delican, Yavuz; Morgul, AvniThis paper presents a high performance 16x16 bit 2's complement multiplier using MOS Current Mode Logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 mu m CMOS technology and VDD of 1.8V. According to our simulations, the highest current circuit works at 800 MHz and consumes 55 mW, while the lowest power operates at 250 MHz and consumes 16 mW. The circuits are either consume less power or operate up to a higher frequency compared to equivalent circuits in the literature. One of the most important advantages of this circuit is the absence of the power supply current spikes which makes the circuit very suitable for mixed mode designs. The multiplier consists of 7,268 transistors while a comparable CMOS multiplier in the literature consists of 13,444 transistors.Öğe High Performance Wideband CMOS CCI and its Application in Inductance Simulator Design(Univ Suceava, Fac Electrical Eng, 2012) Arslan, Emre; Metin, Bilgin; Herencsar, Norbert; Koton, Jaroslav; Morgul, Avni; Cicekoglu, OguzhanIn this paper, a new, differential pair based, low-voltage, high performance and wideband CMOS first generation current conveyor (CCI) is proposed. The proposed CCI has high voltage swings on ports X and Y and very low equivalent impedance on port X due to super source follower configuration. It also has high voltage swings (close to supply voltages) on input and output ports and wideband current and voltage transfer ratios. Furthermore, two novel grounded inductance simulator circuits are proposed as application examples. Using HSpice, it is shown that the simulation results of the proposed CCI and also of the presented inductance simulators are in very good agreement with the expected ones.Öğe High-performance CMOS CCI in a 0.35 ?m CMOS technology and a new all-pass filter application(Tubitak Scientific & Technological Research Council Turkey, 2013) Arslan, Emre; Metin, Bilgin; Cicekoglu, Mehmet Oguzhan; Morgul, AvniA differential pair-based, high-performance, first-generation current conveyor is proposed. The proposed circuit is laid out using the Mentor Graphics IC Station layout editor. The performance characteristics have been determined from HSpice postlayout simulations using the Austria Mikro Systeme 0.35 mu m, 3.3 V process parameters. During the simulations, +/- 1.65 V supply voltages and a 25 mu A biasing current are used. The power consumption is about 1.12 mW. The circuit also has very high voltage swings on ports X and Y, a very small impedance value on port X, high impedance values on ports Y and Z, and high-valued current and voltage transfer bandwidths. It is shown that the presented circuit can satisfy both the low-voltage/low-power and high-frequency performance current conveyor needs of the analog circuit applications. Furthermore, 2 new all-pass filter circuits as application examples are given and a procedure that can be used to search for the opportunities that would result from the use of the modified current conveyors is presented. Some special circuit topologies and new circuit function possibilities can be obtained by redesigning circuits with modified current conveyors, which is not possible with a standard current conveyor. The proposed approach is expected to allow deeper insight into circuit synthesis using modified current conveyors.Öğe ON THE REALIZATION OF HIGH PERFORMANCE CURRENT CONVEYORS AND THEIR APPLICATIONS(World Scientific Publ Co Pte Ltd, 2013) Arslan, Emre; Minaei, Shahram; Morgul, AvniIn this work, a wideband and high-performance CMOS implementation of 2nd-generation current conveyor (CCII) is proposed. The proposed circuit is composed of a high performance voltage follower stage which is based on differential pairs to provide high voltage swings on input and output ports and a current follower stage. It is shown that the proposed voltage follower stage can be used to implement high performance 1st and 3rd-generation current conveyors (CCI and CCIII, respectively) that have very small equivalent impedances on ports X, high equivalent impedances on ports Y and Z and also high-valued voltage and current transfer bandwidths. 2nd and 3rd order filter circuits as well as a half-wave recti filer circuit are given to show the performance and usefulness of the proposed current conveyor circuits. The simulation and experimental results are given to verify the theoretical analyses.Öğe A Redundant Adder Structure Suitable for the New Generation Reconfigurable Fpga Architectures(Beykent Üniversitesi, 2011) Cini, Ugur; Morgul, AvniArithmetic operations are generally slowest operations in digital design which is the bottleneck in most of the systems. Optimizing adder circuits provides faster performance in arithmetic circuits. Field Programmable Gate Arrays (FPGA) are very popular to implement logic circuits. 6-input Look-Up Table (LUT) devices are on the market which dramatically increases the performance. In this paper, alternative addition structures, based on redundant carry-free arithmetic and suitable for 6 input LUT devices, are presented. A new double carry-save addition architecture is proposed, which reduces the critical path of the addition process for 6-input LUT devices.Öğe SELF-BIASING CURRENT CONVEYOR FOR HIGH FREQUENCY APPLICATIONS(World Scientific Publ Co Pte Ltd, 2012) Arslan, Emre; Morgul, AvniA new, self-biasing, differential pair-based and high performance CMOS CCII circuit is proposed which uses no additional biasing voltage or current sources other than the two supply rails. The proposed circuit has high voltage swings on ports X and Y, very low equivalent impedance on port X, high equivalent impedances on ports Y and Z and also wideband voltage and current transfer ratios. The noise analysis of the proposed CCII circuit is studied. Input referred noise voltage at high impedance port Y and input referred noise current at low impedance port X are obtained to form the noise model. Some filter circuits are selected from the literature and their noise comparisons are performed. It is shown that the noise values can differ greatly even though the filter circuits or the passive element values are identical.
