A current-mode multi-valued adder circuit for multi-operand addition
Küçük Resim Yok
Tarih
2011
Yazarlar
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Taylor & Francis Ltd
Erişim Hakkı
info:eu-repo/semantics/closedAccess
Özet
Static CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 mu m technology. As an example of application, an 8 x 8 bit multiplier circuit is designed and simulated using HSPICE.
Açıklama
Anahtar Kelimeler
current-mode logic circuits, multi-valued logic, digital arithmetic, low power digital circuits, multi-operand addition
Kaynak
International Journal Of Electronics
WoS Q Değeri
Q4
Scopus Q Değeri
Q3
Cilt
98
Sayı
6
