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Öğe A current-mode multi-valued adder circuit for multi-operand addition(Taylor & Francis Ltd, 2011) Cini, Ugur; Morgul, AvniStatic CMOS logic circuits have a robust working performance. However, they generate excessive noise when the switching activity is high. Source-coupled logic (SCL) circuits can be an alternative for analogue-friendly design where constant current is driven from the power supply, independent of the switching activity of the circuit. In this work, a compact current-mode multi-operand adder cell, similar to SCL circuits, is designed. The circuit adds up seven input operands using a technique similar to the (7, 3) counter circuit, but with less active elements when compared to a conventional binary (7, 3) counter. The design has comparable power and delay characteristics compared to conventional SCL implementation. The proposed circuit requires only 69 transistors, where 96 transistors are required for the equivalent SCL implementation. Hence the circuit saves on both transistor count and interconnections. The design is optimised for low power operation of high performance arithmetic circuits. The proposed multi-operand adder circuit is designed in UMC 0.18 mu m technology. As an example of application, an 8 x 8 bit multiplier circuit is designed and simulated using HSPICE.Öğe A Redundant Adder Structure Suitable for the New Generation Reconfigurable Fpga Architectures(Beykent Üniversitesi, 2011) Cini, Ugur; Morgul, AvniArithmetic operations are generally slowest operations in digital design which is the bottleneck in most of the systems. Optimizing adder circuits provides faster performance in arithmetic circuits. Field Programmable Gate Arrays (FPGA) are very popular to implement logic circuits. 6-input Look-Up Table (LUT) devices are on the market which dramatically increases the performance. In this paper, alternative addition structures, based on redundant carry-free arithmetic and suitable for 6 input LUT devices, are presented. A new double carry-save addition architecture is proposed, which reduces the critical path of the addition process for 6-input LUT devices.