CMOS non-Foster Circuit Design Using 0.35?m BiCMOS Models by Cancelling the Parasitic Capacitances
Yükleniyor...
Tarih
2022
Yazarlar
Dergi Başlığı
Dergi ISSN
Cilt Başlığı
Yayıncı
Avestia Publishing
Erişim Hakkı
Özet
In this paper, an improved type of CMOS non-Foster circuit with the cross-coupled pair is proposed to produce negative resistance, negative capacitance and negative inductance in the frequency range between 100 MHz and 3 GHz. Non-Foster circuits are also called negative impedance converter (NIC) circuits. The proposed NIC circuit is designed to eliminate the gate-source parasitic capacitances of NMOS transistors which are the core elements of this cross-coupled topology with the help of on-chip inductors. The negative impedance conversion capability of the NIC circuit is shown analytically with the detailed mathematical formulations and proofs. The circuit is also simulated and verified in AWR Design Environment using 0.35µm BiCMOS transistor models comparatively for two cases with and without LC tank sub-circuit. The circuit is tested and verified with the loads of 50? resistance, 5 pF capacitance and 10 nH inductance to be converted negatively. The improvement in the negative impedance conversion rate of the NIC circuit is presented clearly with the impedance-frequency curves. The results show that the performance of the proposed NIC circuit is satisfactory with the help of gate-source parasitic cancellation. Additionally, the preliminary on-chip IC component placement of the NIC circuit using 0.35µm BiCMOS models is proposed for the realization and production.
Açıklama
Anahtar Kelimeler
Non-foster, Negative impedance, CMOS, RF, Matching.
Kaynak
WoS Q Değeri
Scopus Q Değeri
N/A
