Delican, YavuzMorgul, Avni2024-03-132024-03-132009978-1-4244-3895-2https://doi.org/10.1109/ECCTD.2009.5274960https://hdl.handle.net/20.500.12662/3394European Conference on Circuit Theory Design -- AUG 23-27, 2009 -- Antalya, TURKEYThis paper presents a high performance 16x16 bit 2's complement multiplier using MOS Current Mode Logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 mu m CMOS technology and VDD of 1.8V. According to our simulations, the highest current circuit works at 800 MHz and consumes 55 mW, while the lowest power operates at 250 MHz and consumes 16 mW. The circuits are either consume less power or operate up to a higher frequency compared to equivalent circuits in the literature. One of the most important advantages of this circuit is the absence of the power supply current spikes which makes the circuit very suitable for mixed mode designs. The multiplier consists of 7,268 transistors while a comparable CMOS multiplier in the literature consists of 13,444 transistors.eninfo:eu-repo/semantics/closedAccessConference Object10.1109/ECCTD.2009.52749602-s2.0-71249128456+N/A157WOS:000276473700040N/A