Arslan, EmreMorgul, Avni2024-03-132024-03-1320120218-12661793-6454https://doi.org/10.1142/S0218126612500399https://hdl.handle.net/20.500.12662/3689A new, self-biasing, differential pair-based and high performance CMOS CCII circuit is proposed which uses no additional biasing voltage or current sources other than the two supply rails. The proposed circuit has high voltage swings on ports X and Y, very low equivalent impedance on port X, high equivalent impedances on ports Y and Z and also wideband voltage and current transfer ratios. The noise analysis of the proposed CCII circuit is studied. Input referred noise voltage at high impedance port Y and input referred noise current at low impedance port X are obtained to form the noise model. Some filter circuits are selected from the literature and their noise comparisons are performed. It is shown that the noise values can differ greatly even though the filter circuits or the passive element values are identical.eninfo:eu-repo/semantics/closedAccessCurrent conveyorself-biasingfilterArticle10.1142/S02181266125003992-s2.0-848666259085Q321WOS:000308948300004Q4